Information

PIC18F26K20/46K20
DS80000404H-page 4  2008-2013 Microchip Technology Inc.
6. Module: EUSART
The OERR flag of the RCSTA register is reset only
by clearing the CREN bit of the RCSTA register or
by a device Reset. Clearing the SPEN bit of the
RCSTA register does not clear the OERR flag.
Work around
Clear the OERR flag by clearing the CREN bit
instead of clearing the SPEN bit.
Affected Silicon Revisions
7. Module: EUSART
In Asynchronous Receive mode when the RX
input goes low after an Idle period and stays low
for less than 1/16th bit period, then that event will
be correctly detected as an invalid Start bit. If the
RX input goes low a second time, less than one full
bit time after the leading edge of the first invalid
Start time, then the low transition of the RCIDL
Status bit will be improperly delayed by one full bit
time following that second edge. If the second
pulse is also an invalid Start bit then the RCIDL will
remain low indefinitely until either a valid Start bit
occurs or the EUSART is reset.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by
resetting the EUSART receiver. The EUSART
receiver is reset when either the SPEN bit or
CREN bit of the RCSTA register is cleared.
Affected Silicon Revisions
8. Module: System Clocks
HFINTOSC output frequency may have up to 1%
short term frequency instability beyond the
maximum and minimum limits shown in the data
sheet.
Work around
Use the HS, XT or EC clock modes.
Affected Silicon Revisions
9. Module: Data EEPROM Memory
The write/erase endurance of data EEPROM
memory is limited to 10K cycles.
Work around
Use the error correction method that stores data in
multiple locations.
Affected Silicon Revisions
10. Module: Program Flash Memory
The write/erase endurance of the PFM is limited to
1K cycles when V
DD is above 3V. Endurance
degrades when V
DD is below 3V.
Work around
For data tables in program Flash memory use the
error correction method that stores data in multiple
locations.
Affected Silicon Revisions
11. Module: PORTB Interrupt-on-Change
Setting a PORTB interrupt-on-change enable bit of
the IOCB register while the corresponding PORTB
input is high will cause an RBIF interrupt.
Work around
Set the IOCB bits to the desired configuration then
read PORTB to clear the mismatch latches.
Finally, clear the RBIF bit before setting the RBIE
bit.
Affected Silicon Revisions
B2 B3 B5 B6
XX
X X
B2 B3 B5 B6
XX
X X
B2 B3
B5 B6
X
B2 B3 B5 B6
XX
X X
B2 B3 B5 B6
XX
X X
B2 B3
B5 B6
XX
X X