Information

 2008-2013 Microchip Technology Inc. DS80000404H-page 3
PIC18F26K20/46K20
Silicon Errata Issues
1. Module: ECCP
Changing direction in Full-Bridge mode inserts a
dead-band time of 4/F
OSC * TMR2 prescale
instead of 1/F
OSC * TMR2 prescale as specified in
the data sheet.
Work around
None.
Affected Silicon Revisions
2. Module: ECCP
ECCP – In Full-Bridge mode when
PR2 = CCPR1L and DC1B[1:0] <>'00' and the
direction is changed, then the dead time before the
modulated output starts is compromised. The
modulated signal improperly starts immediately
with the direction change and stays on for
T
OSC *TMR2Presale* DC1B[1:0].
Work around
Avoid changing direction when the duty cycle is
within three least significant steps of 100% duty
cycle. Instead, clear the DC1B[1:0] bits before the
direction change and then set them to the desired
value after the direction change is complete.
Affected Silicon Revisions
3. Module: MSSP SPI
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011) and the CKE bit of the
SSPSTAT register is ‘1’, then the first SDO data bit
and SCK non-idle edge occur simultaneously.
Also, the first SCK non-idle level may be short.
Work around
Use clock mode other than Timer2/2.
Affected Silicon Revisions
4. Module: MSSP SPI
In SPI Master mode, when the CKE bit of the
SSPSTAT register is cleared and the SMP bit of
the SSPSTAT register is set, then the last bit of the
incoming data stream (bit 0) at the SDI pin will not
be sampled properly.
Work around
None.
Affected Silicon Revisions
5. Module: MSSP (Master I
2
C™ Mode)
In Master I
2
C Receive mode, if a Stop condition
occurs in the middle of an address or data
reception, then the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condition,
then 9 additional clocks will be generated followed
by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches, which may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop condi-
tion and resulting stuck RCEN bit. Clear stuck
RCEN bit by clearing SSPEN bit of SSPCON1.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B6).
B2 B3
B5 B6
XX
X X
B2 B3 B5 B6
XX
X X
B2 B3 B5 B6
XX
X X
B2 B3
B5 B6
XX
X X
B2 B3
B5 B6
XX
X X