Information

PIC18F26K20/46K20
DS80000404H-page 2  2008-2013 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
B2 B3 B5 B6
ECCP Full-Bridge 1. Dead-band time is 4/F
OSC instead
of 1/F
OSC.
XXXX
ECCP Full-Bridge 2. Compromised dead band. X X X X
MSSP SPI SPI Clock 3. Improper start in Timer2/2 Clock
mode.
XXXX
MSSP SPI SPI Master 4. Improper sampling of last bit. X X X X
MSSP (Master I
2
C™
Mode)
I
2
C™ Master 5. Improper handling of Stop event. X X X X
EUSART OERR Flag 6. Clearing SPEN bit does not clear
OERR flag.
XXXX
EUSART BAUDCON 7. RCIDL may improperly stay low. X X X X
System Clocks HFINTOSC 8. Frequency instability. X
Data EEPROM Memory Endurance 9. Endurance limited to 10K cycles. X X X X
Program Flash Memory Endurance 10. Endurance limited to 1K cycles. X X X X
PORTB Interrupt-on-
Change
Interrupt-on-
change
11. False interrupt when setting inter-
rupt enable.
XXXX
ADC ADC Conversion 12. ADC conversion may be limited to
half scale.
XX
Interrupt-on-Change Interrupt-on-
change interrupt
when in Sleep
13. False interrupt when waking from
Sleep.
XXXX
Capture/Compare/PWM Capture mode 14. Weak pull-up disabled in Capture
mode on CCP2
XXXX
Low-Voltage Detect LVD in Sleep 15. LVD erroneously triggers upon
wake-up from Sleep if band gap is
disabled in Sleep mode.
XXXX
Resets (BOR) Brown-out Reset 16. An unexpected Reset may occur if
the Brown-out Reset module (BOR)
is disabled, and then re-enabled.
XXXX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.