Datasheet

© 2008 Microchip Technology Inc. DS80379A-page 3
PIC18F26K20/46K20
19. Module: Clocks
EC Mode operation is limited to a maximum of
48 MHz.
Work around
Use HS Clock mode for external clocking above
48 MHz.
20. Module: Comparators
Comparator input offset voltage is ± 25 mV and
may degrade over the lifetime of the part
accelerated by high temperature. The offset voltage
increases as the common-mode voltage decreases
with the following characteristics: Offset is ± 25 mV
when the common-mode voltage is V
DD; The offset
is up to ± 50 mV when the common-mode voltage
is V
DD/2; The offset is greater than ± 50 mV when
the common-mode voltage is 0V.
Work around
None.
21. Module: Comparators
When the CxON bit is clear, the output from the
comparator will be properly forced to zero, but the
CxPOL bit will improperly have no effect on the
CxOUT bit. This prevents presetting the compara-
tor change-on-interrupt mismatch latches as
described in the data sheet.
Work around
Configure one of the unused comparator input
channels as a digital output. Use that digital output
to manipulate the comparator output to the desired
CxOUT non-interrupt level. When the comparator
is then set to the desired inputs, the mismatch
latches will be preset to the non-interrupt level and
the CxIF flag can then be cleared.
22. Module: Data EEPROM Memory
The write/erase endurance of Data EE Memory is
limited to 10K cycles.
Work around
Use error correction method that stores data in
multiple locations.
23. Module: Program Flash Memory
The write/erase endurance of the PFM is limited to
1K cycles when V
DD is above 3V. Endurance
degrades when V
DD is below 3V.
Work around
For data tables in program Flash memory, use the
error correction method that stores data in multiple
locations.
24. Module: Input/Output (PIC18F26K20
only)
Reading PORTE bit 3 always returns 0.
Work around
None.
25. Module: Timer 1
In Asynchronous Counter mode, a false interrupt
may occur on the first rising T1CKI clock edge
after writing the TMR1H or TMR1L register.
Work around
Examine the TMR1H:TMR1L register pair in the
Interrupt Service Routine (ISR). If the
TMR1H:TMR1L register pair is less than the
preset value then service the interrupt. Otherwise,
disregard the interrupt and only clear the Timer1
interrupt flag.