Datasheet

PIC18F26K20/46K20
DS80379A-page 2 © 2008 Microchip Technology Inc.
9. Module: MSSP SPI
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
data stream (bit 0) at the SDI pin will not be
sampled properly.
Work around
None.
10. Module: MSSP SPI
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift register
on every high-to-low transition of the SS
pin.
Work around
Avoid using the SS pin when the CKE bit is set and
the MSSP is configured for SPI Master mode.
11. Module: MSSP SPI
When SPI is enabled in Master mode with
CKE = 1 and CKP = 0, a 1/F
OSC wide pulse will
occur on the SCK pin.
Work around
Configure the SCK pin as an input until after the
MSSP is setup.
12. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
output will be skewed by one baud clock count.
Work around
High values of SPBRG will minimize the effect of
this anomaly.
13. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
previous character is still in the TX shift register, the
LS bit of the TXREG character may be corrupted
during transmission.
Work around
When SPBRG is set to 3, wait until the TRMT bit of
the TXSTA register is set before loading TXREG
with the next character to be transmitted.
14. Module: EUSART
In Synchronous Master mode, if the SPBRG
register is equal to 0, when the TXEN bit is set,
then writing to TXREG will properly start
transmission. However, the clock will be
improperly out of phase with the data bits and the
clock will not stop at the end of the character
transmission.
Work around
Set SPBRG register to non-zero value before
setting the TXEN bit.
15. Module: System Clocks
HFINTOSC output frequency is 16 MHz ± 3%,
25°C to 85°C.
Work around
None.
16. Module: POR/BOR
The POR rearm voltage may be below the low end
of the BOR range causing unexpected code
execution below the BOR range.
Work around
Use external power monitor to hold device in
Reset below 1.1 Volts.
17. Module: POR
The POR may release around 0.8 volts (below the
POR rearm voltage of 1.2V nominal) when V
DD
rises from below either 0.60V when BOR is not
enabled, or 0.33V when BOR is enabled.
Work around
Use Power-up Timer when operating with the EC,
EXTRC or HFINTOSC oscillator modes. Ensure
that V
DD rise time is less than the Power-up Timer
time.
18. Module: POR
The part may hang in the Reset state when VDD
falls to the POR rearm threshold of approximately
1.2 volts then rises at a rate faster than 7500 volts
per second to the operating range. Recovery from
the hung state is possible only by first lowering
V
DD to below the POR rearm threshold followed by
raising V
DD to the operating range.
Work around
Slow VDD rise time by adding series resistance
between the voltage supply and the V
DD pin. VDD
bypassing should remain on the pin side of the
series resistor.