Datasheet
© 2008 Microchip Technology Inc. DS80379A-page 1
PIC18F26K20/46K20
The PIC18F26K20/46K20 parts you have received
conform functionally to the Device Data Sheet
(DS41303C) and the Programming Specification
(DS41297D), except for the anomalies described
below.
All problems listed here will be addressed in future
revisions of the PIC18F26K20/46K20 silicon.
1. Module: ECCP
Changing the CCP1M<3:0> bits of CCP1CON
may cause the CCPR1H and CCPR1L registers to
capture the value of Timer1.
Work around
Halt Timer1 before changing ECCP mode. Reload
Timer1 with desired value after ECCP is setup and
before Timer1 is restarted.
2. Module: ECCP
Changing direction in Full-Bridge mode does not
insert dead time between changing the active
drivers in common legs of the bridge.
Work around
None.
3. Module: MSSP I
2
C™
Slew rate is slower than I
2
C specifications when
the SLRCON<2> bit is set.
Work around
Clear SLRCON<2> bit when using the I
2
C
peripheral.
4. Module: ADC
Offset error is 3 LSb typical, 7 LSb maximum,
including an acquisition time dependent
component (~2 LSb).
Work around
The time dependent error is insignificant when the
time between conversions is less than 100 ms.
When the time since the previous conversion is
greater than 100 ms then take two ADC
conversions and discard the first.
5. Module: MSSP I
2
C
If a new address byte is received while the BF flag
is set, the SSPOV bit is set and an ACK is not
generated, both of which are proper operation. If
only the SSPOV bit is set (BF flag was cleared)
and a matching address is clocked in, that
received byte will be loaded into the SSPBUF
register and an ACK will be generated, both of
which are improper operation.
Work around
None.
6. Module: MSSP I
2
C
In Master I
2
C mode, when a slave device releases
the clock after holding it low (clock stretching), the
pulse width of the first high clock cycle may be
shorter than half the clock period.
Work around
None.
7. Module: MSSP I
2
C
In Master I
2
C mode, baud rates obtained by
setting SSPADD to a value less than 0x03 will
cause unexpected operation.
Work around
Ensure SSPADD is set to a value greater than or
equal to 0x04.
8. Module: MSSP SPI
When the SPI clock is configured for Timer2 output/2
(SSPCON1<3:0> = 0 011 ), the first SPI high time
may be short.
Work around
Option 1: Ensure TMR2 value rolls over to zero
immediately before writing to SSPBUF.
Option 2
: Turn Timer2 off and clear TMR2 before
writing SSPBUF. Enable TMR2 after SSPBUF is
written.
PIC18F26K20/46K20 Rev. A4 Through A5 Silicon/Data Sheet Errata