Information

PIC18F2XK20/4XK20
DS41303G-page 346  2010 Microchip Technology Inc.
RETFIE Return from Interrupt
Syntax: RETFIE {s}
Operands: s  [0,1]
Operation: (TOS)  PC,
1  GIE/GIEH or PEIE/GIEL,
if s = 1
(WS)  W,
(STATUSS)  Status,
(BSRS)  BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
Status and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
No
operation
No
operation
No
operation
Example
: RETFIE 1
After Interrupt
PC = TOS
W=WS
BSR = BSRS
Status = STATUSS
GIE/GIEH, PEIE/GIEL = 1
RETLW Return literal to W
Syntax: RETLW k
Operands: 0  k  255
Operation: k  W,
(TOS)  PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 1100 kkkk kkkk
Description: W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
POP PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
Example
:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
W = 07h
After Instruction
W = value of kn