Information

PIC18F2XK20/4XK20
DS41303G-page 212  2010 Microchip Technology Inc.
FIGURE 17-11: I
2
C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA SCL SSPIF BF (SSPSTAT<0>)
S
123456789 123456789 12345 7 89
P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8
R/W=1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared by software
Bus master
terminates transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when SSPADD is updated with low byte of address
UA (SSPSTAT<1>)
Clock is held low until update of SSPADD has taken place
UA is set indicating that the SSPADD needs to be updated
UA is set indicating that SSPADD needs to be updated
Cleared by hardware when SSPADD is updated with high byte of address.
SSPBUF is written with contents of SSPSR
Dummy read of SSPBUF to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF to clear BF flag
Sr
Cleared by software
Write of SSPBUF
initiates transmit
Cleared by software
Completion of clears BF flag
CKP (SSPCON1<4>)
CKP is set by software
CKP is automatically cleared by hardware, holding SCL low
Clock is held low until update of SSPADD has taken place
data transmission
Clock is held low until CKP is set to ‘1’
third address sequence BF flag is clear at the end of the