Information

 2010 Microchip Technology Inc. DS41303G-page 211
PIC18F2XK20/4XK20
FIGURE 17-10: I
2
C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA SCL SSPIF BF (SSPSTAT<0>)
S
123456789 123456789 12345 789
P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7 D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared by software
D2
6
(PIR1<3>)
Cleared by software
Receive Second Byte of Address
Cleared by hardware when SSPADD is updated with low byte of address
UA (SSPSTAT<1>)
Clock is held low until update of SSPADD has taken place
UA is set indicating that the SSPADD needs to be updated
UA is set indicating that SSPADD needs to be updated
Cleared by hardware when SSPADD is updated with high byte of address
SSPBUF is written with contents of SSPSR
Dummy read of SSPBUF to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master terminates transfer
D2
6
ACK
Cleared by software
Cleared by software
SSPOV (SSPCON1<6>)
SSPOV is set because SSPBUF is still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until update of SSPADD has taken place