Information

 2010 Microchip Technology Inc. DS41303G-page 141
PIC18F2XK20/4XK20
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTD
(1)
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 62
LATD
(1)
PORTD Data Latch Register (Read and Write to Data Latch) 62
TRISD
(1)
PORTD Data Direction Control Register 62
PORTE
— — — — RE3 RE2
(1)
RE1
(1)
RE0
(1)
62
LATE
(1)
— — — — — LATE Data Output bits 62
TRISE
(1)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 62
SLRCON
— — —SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 63
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 62
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 62
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 62
ANSEL ANS7
(1)
ANS6
(1)
ANS5
(1)
ANS4 ANS3 ANS2 ANS1 ANS0 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Unimplemented on PIC18F2XK20 devices.