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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 8-Bit 48 MHz I/O number 24

 2008-2013 Microchip Technology Inc. DS80000404H-page 1

PIC18F26K20/46K20

The PIC18F26K20/46K20 family devices that you have

received conform functionally to the current Device

Data Sheet (DS41303G), except for the anomalies

described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Tab le 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC18F26K20/46K20 silicon.

Data Sheet clarifications and corrections start on page

7, following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s pro-

grammers, debuggers, and emulation tools, which are

available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level

using MPLAB IDE in conjunction with a hardware

debugger:

1. Using the appropriate interface, connect the

device to the hardware debugger.

2. Open an MPLAB IDE project.

3. Configure the MPLAB IDE project for the

appropriate device and hardware debugger.

4. Based on the version of MPLAB IDE you are

using, do one of the following:

a) For MPLAB IDE 8, select Programmer >

Reconnect.

b) For MPLAB X IDE, select Window >

Dashboard and click the Refresh Debug

Tool Status icon ( ).

5. Depending on the development tool used, the

part number and Device Revision ID value

appear in the Output window.

The DEVREV values for the various PIC18F26K20/

46K20 silicon revisions are shown in Tabl e 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon revi-

sion (B6).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

(11-bit)

Revision ID for Silicon Revision

(2)

(5-bit)

B2 B3 B5 B6

PIC18F26K20 100h 0x09 0x0A 0x0C 0x0D

PIC18F46K20 101h 0x09 0x0A 0x0C 0x0D

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID:DEVREV”.

2: Refer to the “PIC18F2XK20/4XK20 Flash Programming Specification” (DS41297) for detailed information

on Device and Revision IDs for your specific device.

PIC18F26K20/46K20 Rev. B2/B3/B5/B6 Silicon Errata

and Data Sheet Clarification

Summary of content (10 pages)

PAGE 1
PIC18F26K20/46K20 PIC18F26K20/46K20 Rev. B2/B3/B5/B6 Silicon Errata and Data Sheet Clarification The PIC18F26K20/46K20 family devices that you have received conform functionally to the current Device Data Sheet (DS41303G), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1.
PAGE 2
PIC18F26K20/46K20 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary B2 B3 B5 B6 ECCP Full-Bridge 1. Dead-band time is 4/FOSC instead of 1/FOSC. X X X X ECCP Full-Bridge 2. Compromised dead band. X X X X MSSP SPI SPI Clock 3. Improper start in Timer2/2 Clock mode. X X X X MSSP SPI SPI Master 4. Improper sampling of last bit. X X X X MSSP (Master I C™ Mode) I2C™ Master 5. Improper handling of Stop event.
PAGE 3
PIC18F26K20/46K20 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B6). 3. Module: MSSP SPI When the SPI clock is configured for Timer2/2 (SSPCON1<3:0> = 0011) and the CKE bit of the SSPSTAT register is ‘1’, then the first SDO data bit and SCK non-idle edge occur simultaneously.
PAGE 4
PIC18F26K20/46K20 6. Module: EUSART The OERR flag of the RCSTA register is reset only by clearing the CREN bit of the RCSTA register or by a device Reset. Clearing the SPEN bit of the RCSTA register does not clear the OERR flag. 9. Module: Data EEPROM Memory The write/erase endurance of data EEPROM memory is limited to 10K cycles. Work around Work around Use the error correction method that stores data in multiple locations. Clear the OERR flag by clearing the CREN bit instead of clearing the SPEN bit.
PAGE 5
PIC18F26K20/46K20 12. Module: ADC 14. Module: Capture/Compare/PWM After extended stress the Most Significant bit (MSb) of the ADC conversion result can become stuck at ‘0’. Conversions resulting in code 511 or less are still accurate, but conversions that should result in codes greater than 511 are instead pinned at 511. The potential for failures is a function of several factors: • The potential for failures increases over the life of the part.
PAGE 6
PIC18F26K20/46K20 16. Module: Resets (BOR) An unexpected Reset may occur if the Brown-out Reset module (BOR) is disabled, and then reenabled when the Fixed Voltage Reference is not enabled (CVRCON2<7> = 0). This issue affects BOR modes: BOREN<1:0> = 10 and BOREN<1:0> = 01. In both of these modes, if the BOR module is re-enabled while the device is active, unexpected Resets may be generated. Work around If BOR is required, and power consumption is not an issue, use BOREN<1:0> = 11.
PAGE 7
PIC18F26K20/46K20 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41303G): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Electrical Characteristics Parameter D026 in Table 26-8 on page 376 of the data sheet lists the maximum ADC delta current at 1.8V as 290 µA. The correct value should be 360 µA.
PAGE 8
PIC18F26K20/46K20 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (9/2008) Initial release of this document. Rev B Document (5/2009) Updated Errata to new format. Added Module 5. MSSP Master I2C Mode; Added Module 6. EUSART; Added Module 12. ADC. Clarifications/Corrections to the Data Sheet: Removed Modules 1-3. Rev C Document (6/2009) Revised Table 1: Silicon DEVREV Values.
PAGE 9
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 10
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