Datasheet

PIC18F46J50 FAMILY
DS39931D-page 530  2011 Microchip Technology Inc.
TABLE 30-32: A/D CONVERSION REQUIREMENTS
FIGURE 30-24: USB SIGNAL TIMING
TABLE 30-33: USB LOW-SPEED TIMING REQUIREMENTS
TABLE 30-34: USB FULL-SPEED REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period 0.7 25.0
(1)
sTOSC based, VREF  3.0V
131 TCNV Conversion Time
(not including acquisition time)
(2)
11 12 TAD
132 TACQ Acquisition Time
(3)
1.4 — s-40C to +85C
135 TSWC Switching Time from Convert  Sample — (Note 4)
137 T
DIS Discharge Time 0.2 — s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
TLR Transition Rise Time 75 — 300 ns CL = 200 to 600 pF
TLF Transition Fall Time 75 — 300 ns CL = 200 to 600 pF
T
LRFM Rise/Fall Time Matching 80 — 125 %
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
T
FR Transition Rise Time 4 — 20 ns CL = 50 pF
T
FF Transition Fall Time 4 — 20 ns CL = 50 pF
T
FRFM Rise/Fall Time Matching 90 — 111.1 %
VCRS
USB Data Differential Lines
90%
10%
TLR, TFR
TLF, TFF