Datasheet

PIC18F46J50 FAMILY
DS39931D-page 146  2011 Microchip Technology Inc.
10.5 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable as an
input or an output.
EXAMPLE 10-5: INITIALIZING PORTD
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by setting bit, RDPU (PORTE<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR. The integrated weak pull-ups consist of a semi-
conductor structure similar to, but somewhat different,
from a discrete resistor. On an unloaded I/O pin, the
weak pull-ups are intended to provide logic high indica-
tion, but will not necessarily pull the pin all the way to
V
DD levels.
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB.
Note: PORTD is available only on 44-pin devices.
Note: On a POR, these pins are configured as
digital inputs.
CLRF LATD ;Initialize output data
;levels for output pins
MOVLW 0x7F ;Example value used to
;initialize data direction
MOVWF TRISD ;RD0-RD6 as inputs
;RD7 as output
TABLE 10-9: PORTD I/O SUMMARY
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/PMD0/
SCL2
RD0 1 I ST PORTD<0> data input.
0 O DIG LATD<0> data output.
PMD0 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
SCL2 1 II
2
C/
SMB
I
2
C™ clock input (MSSP2 module); input type depends on
module setting.
0 OI
2
CI
2
C clock output (MSSP2 module); takes priority over port data.
RD1/PMD1/
SDA2
RD1 1 I ST PORTD<1> data input.
0 O DIG LATD<1> data output.
PMD1 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
SDA2 1 II
2
C/
SMB
I
2
C data input (MSSP2 module); input type depends on
module setting.
0 OI
2
CI
2
C data output (MSSP2 module); takes priority over port data.
RD2/PMD2/
RP19
RD2 1 I ST PORTD<2> data input.
0 O DIG LATD<2> data output.
PMD2 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP19 1 I ST Remappable Peripheral Pin 19 input.
0 O DIG Remappable Peripheral Pin 19 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
2
C/SMB = I
2
C/SMBus
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).