Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 551
PIC18F47J13 FAMILY
RPOR8 (Peripheral Pin Select Output 8) ................. 172
RPOR9 (Peripheral Pin Select Output 9) ................. 173
RTCCAL (RTCC Calibration) ................................... 240
RTCCFG (RTCC Configuration) .............................. 239
SECONDS (Seconds Value) .................................... 245
SPI Mode (MSSP) .................................................... 293
SSPxCON1 (MSSPx Control 1, I
2
C Mode) .............. 312
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 294
SSPxCON2 (MSSPx Control 2,
I
2
C Master Mode) ............................................. 313
SSPxCON2 (MSSPx Control 2,
I
2
C Slave Mode) ............................................... 314
SSPxMSK (I
2
C Slave Address Mask) ...................... 314
SSPxSTAT (MSSPx Status, I
2
C Mode) ................... 311
SSPxSTAT (MSSPx Status, SPI Mode) .................. 293
STATUS ................................................................... 100
STKPTR (Stack Pointer) ............................................ 84
T0CON (Timer0 Control) .......................................... 205
T1CON (Timer1 Control) .......................................... 209
T1GCON (Timer1 Gate Control) .............................. 210
T2CON (Timer2 Control) .......................................... 219
TxCON (Timer3/5 Control) ....................................... 222
TxCON (Timer4/6/8 Control) .................................... 234
TxGCON (Timer3/5 Gate Control) ........................... 223
TXSTAx (Transmit Status and Control) ................... 346
WDTCON (Watchdog Timer Control) ....................... 425
WKDY (Weekday Value) .......................................... 244
YEAR (Year Value) .................................................. 243
RESET ............................................................................. 463
Reset .................................................................................. 65
Brown-out Reset ........................................................ 67
Brown-out Reset (BOR) ............................................. 65
Configuration Mismatch (CM) .................................... 65
Configuration Mismatch Reset ................................... 68
Deep Sleep ................................................................ 65
Fast Register Stack (FSR) ......................................... 85
MCLR
......................................................................... 67
MCLR
Reset, During Power-Managed Modes ........... 65
MCLR
Reset, Normal Operation ................................ 65
Power-on Reset ......................................................... 67
Power-on Reset (POR) .............................................. 65
Power-up Timer ......................................................... 68
RESET Instruction ..................................................... 65
Stack Full Reset ......................................................... 65
Stack Underflow Reset .............................................. 65
State of Registers ...................................................... 70
Watchdog Timer (WDT) Reset ................................... 65
Resets .............................................................................. 415
Brown-out Reset (BOR) ........................................... 415
Oscillator Start-up Timer (OST) ............................... 415
Power-on Reset (POR) ............................................ 415
Power-up Timer (PWRT) ......................................... 415
RETFIE ............................................................................ 464
RETLW ............................................................................. 464
RETURN .......................................................................... 465
Return Address Stack ........................................................ 83
Associated Registers ................................................. 83
Revision History ............................................................... 541
RLCF ................................................................................ 465
RLNCF ............................................................................. 466
RRCF ............................................................................... 466
RRNCF ............................................................................. 467
RTCC
Alarm ....................................................................... 253
Configuring ...................................................... 253
Interrupt ........................................................... 254
Mask Settings .................................................. 253
Alarm Value Register Mappings (ALRMVAL) .......... 246
Control Registers ..................................................... 239
Control/Value Register Maps ................................... 255
Low-Power Modes ................................................... 254
Operation
Calibration ....................................................... 252
Clock Source ................................................... 250
Digit Carry Rules ............................................. 250
General Functionality ....................................... 251
Leap Year ........................................................ 251
Register Mapping ............................................ 251
ALRMVAL ................................................ 252
RTCVAL .................................................. 252
Safety Window for Register Reads
and Writes ............................................... 251
Write Lock ........................................................ 251
Peripheral Module Disable (PMD) Register ............. 255
Register Interface .................................................... 249
Reset ....................................................................... 254
Device .............................................................. 254
Power-on Reset (POR) .................................... 254
Value Register Mappings (RTCVAL) ....................... 243
RTCEN Bit Write .............................................................. 249
S
SCKx ................................................................................ 292
SDIx ................................................................................. 292
SDOx ............................................................................... 292
SEC_IDLE Mode ............................................................... 52
SEC_RUN Mode ................................................................ 49
Serial Clock, SCKx .......................................................... 292
Serial Data In (SDIx) ........................................................ 292
Serial Data Out (SDOx) ................................................... 292
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 467
Shoot-Through Current .................................................... 285
Slave Select (SSx
) ........................................................... 292
SLEEP ............................................................................. 468
Software Simulator (MPLAB SIM) ................................... 485
Special Event Trigger. See Compare (CCP Module).
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ........................................... 415
SPI Mode (MSSP) ........................................................... 292
Associated Registers ............................................... 301
Bus Mode Compatibility ........................................... 300
Clock Speed, Interactions ........................................ 300
DMA Module ............................................................ 302
I/O Pin Considerations ..................................... 302
Idle, Sleep Considerations ............................... 302
RAM to RAM Copy .......................................... 302
Registers ......................................................... 302
Effects of a Reset .................................................... 300
Enabling SPI I/O ...................................................... 296
Master Mode ............................................................ 297
Master/Slave Connection ......................................... 296
Operation ................................................................. 295
Open-Drain Output Option ............................... 295