Datasheet

PIC18F47J13 FAMILY
DS39974A-page 412 Preliminary  2010 Microchip Technology Inc.
REGISTER 26-3: CTMUICON: CTMU CURRENT CONTROL REGISTER (ACCESS FB1h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 ITRIM<5:0>: Current Source Trim bits
011111 = Maximum positive change (+62% typ.) from nominal current
011110
.
.
.
000001 = Minimum positive change (+2% typ.) from nominal current
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change (-2% typ.) from nominal current
.
.
.
100010
100001 = Maximum negative change (-62% typ.) from nominal current
bit 1-0 IRNG<1:0>: Current Source Range Select bits
11 = 100  Base current
10 = 10  Base current
01 = Base current level (0.55 A nominal)
00 = Current source disabled
REGISTER 26-4: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h)
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CTMUDS — — — — —
SPI2OD SPI1OD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CTMUDS: CTMU Pulse Delay Enable bit
1 = Pulse delay input for CTMU enabled on pin RA1
bit 6-2 Unimplemented: Read as ‘0’
bit 1 SPI2OD: SPI2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 0 SPI1OD: SPI1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled