Datasheet

PIC18F47J13 FAMILY
DS39974A-page 296 Preliminary  2010 Microchip Technology Inc.
20.3.4 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPxCON1 registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx
pins as
serial port pins. For the pins to behave as the serial port
function, the appropriate TRISx bits, PCFGx bits and
Peripheral Pin Select registers (if using MSSP2) should
be correctly initialized prior to setting the SSPEN bit.
A typical SPI serial port initialization process follows:
• Initialize the ODCON3 register (optional
open-drain output control)
• Initialize the remappable pin functions (if using
MSSP2, see Section 10.7 “Peripheral Pin
Select (PPS)”)
• Initialize the SCKx/LAT value to the desired Idle
SCKx level (if master device)
• Initialize the SCKx/PCFGx bit (if in Slave mode
and multiplexed with the ANx function)
• Initialize the SCKx/TRISx bit as an output (Master
mode) or input (Slave mode)
• Initialize the SDIx/PCFGx bit (if SDIx is
multiplexed with the ANx function)
• Initialize the SDIx/TRISx bit
• Initialize the SSx
/PCFG bit (if in Slave mode and
multiplexed with the ANx function)
• Initialize the SSx
/TRISx bit (Slave modes)
• Initialize the SDOx/TRISx bit
• Initialize the SSPxSTAT register
• Initialize the SSPxCON1 register
• Set the SSPEN bit to enable the module
Any MSSP1 serial port function that is not desired may
be overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value. If
individual MSSP2 serial port functions will not be used,
they may be left unmapped.
20.3.5 TYPICAL CONNECTION
Figure 20-2 illustrates a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time. Whether
the data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
• Master sends valid data–Slave sends dummy
data
• Master sends valid data–Slave sends valid data
• Master sends dummy data–Slave sends valid data
FIGURE 20-2: SPI MASTER/SLAVE CONNECTION
Note: When MSSP2 is used in SPI Master
mode, the SCK2 function must be config-
ured as both an output and an input in the
PPS module. SCK2 must be initialized as
an output pin (by writing 0x0A to one of the
RPORx registers). Additionally, SCK2IN
must also be mapped to the same pin by
initializing the RPINR22 register. Failure to
initialize SCK2/SCK2IN as both output
and input will prevent the module from
receiving data on the SDI2 pin, as the
module uses the SCK2IN signal to latch
the received data.
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1
SCKx
SPI Master SSPM<3:0> = 00xxb
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPxSR)
LSb
MSb
SDIx
SDOx
PROCESSOR 2
SCKx
SPI Slave SSPM<3:0> = 010xb
Serial Clock