Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 287

PIC18F47J13 FAMILY

(1, ACCESS FBFh; 2, FB9h; 3, BANKED F1Ah)

(1)

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1

CMPL1 CMPL0

— STRSYNC STRD STRC STRB STRA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits

1 = Modulated output pin toggles between PxA and PxB for each period

0 = Complementary output assignment is disabled; the STRD:STRA bits are used to determine Steer-

ing mode

bit 5 Unimplemented: Read as ‘0’

bit 4 STRSYNC: Steering Sync bit

1 = Output steering update occurs on the next PWM period

0 = Output steering update occurs at the beginning of the instruction cycle boundary

bit 3 STRD: Steering Enable D bit

1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxD pin is assigned to a port pin

bit 2 STRC: Steering Enable C bit

1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxC pin is assigned to a port pin

bit 1 STRB: Steering Enable B bit

1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxB pin is assigned to a port pin

bit 0 STRA: Steering Enable A bit

1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxA pin is assigned to a port pin

Note 1: The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2> = 11 and

PxM<1:0> = 00.