Datasheet

PIC18F47J13 FAMILY
DS39974A-page 262 Preliminary  2010 Microchip Technology Inc.
18.1.2 OPEN-DRAIN OUTPUT OPTION
When operating in Output mode (the Compare or PWM
modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the
CCPxOD bits (ODCON1<7:0> and ODCON2<3:2>).
Setting the appropriate bit configures the pin for the
corresponding module for open-drain operation.
18.2 Capture Mode
In Capture mode, the CCPR4H:CCPR4L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP4 pin, RB4. An event
is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The event is selected by the mode select bits,
CCP4M<3:0> (CCP4CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP4IF (PIR4<1>),
is set. (It must be cleared in software.) If another
capture occurs before the value in register, CCPR4, is
read, the old captured value is overwritten by the new
captured value.
Figure 18-1 shows the Capture mode block diagram.
18.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRISx direction bit.
18.2.2 TIMER1/3/5 MODE SELECTION
For the available timers (1/3/5) to be used for the capture
feature, the used timers must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the CCPTMRSx registers. (See Section 18.1.1 “CCP
Modules and Timer Resources”.)
Details of the timer assignments for the CCP modules
are given in Table 18-2 and Table 18-3.
FIGURE 18-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If RB4 is configured as a CCP4 output, a
write to the port causes a capture condition.
CCPR5H CCPR5L
TMR1H TMR1L
Set CCP5IF
TMR5
Enable
Q1:Q4
CCP5CON<3:0>
CCP5 Pin
Prescaler
 1, 4, 16
and
Edge Detect
TMR1
Enable
C5TSEL0
C5TSEL0
CCPR4H
CCPR4L
TMR1H TMR1L
Set CCP4IF
TMR3
Enable
CCP4CON<3:0>
CCP4 Pin
Prescaler
 1, 4, 16
TMR3H TMR3L
TMR1
Enable
C4TSEL0
C4TSEL1
C4TSEL0
C4TSEL1
TMR5H TMR5L
and
Edge Detect
4
4
4
Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 18-2 and Table 18-3.