Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 259
PIC18F47J13 FAMILY
REGISTER 18-3: CCPTMRS2: CCP4-10 TIMER SELECT 2 REGISTER (BANKED F50h)
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 C10TSEL0: CCP10 Timer Selection bit
0 = CCP10 is based off of TMR1/TMR2
1 = Reserved; do not use
bit 3 Unimplemented: Read as ‘0’
bit 2 C9TSEL0: CCP9 Timer Selection bit
0 = CCP9 is based off of TMR1/TMR2
1 = CCP9 is based off of TMR1/TMR4
bit 1-0 C8TSEL<1:0>: CCP8 Timer Selection bits
00 = CCP8 is based off of TMR1/TMR2
01 = CCP8 is based off of TMR1/TMR4
10 = CCP8 is based off of TMR1/TMR6
11 = Reserved; do not use