Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 15
PIC18F47J13 FAMILY
FIGURE 1-2: PIC18F4XJ13 (44-PIN) BLOCK DIAGRAM
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
8
8
3
W
8
8
8
Instruction
Decode and
Control
Data Latch
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
Address Latch
Program Memory
Data Latch
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
ROM Latch
PCLATU
PCU
Instruction Bus <16>
STKPTR
Bank
State Machine
Control Signals
Decode
System Bus Interface
AD<15:0>, A<19:16>
(Multiplexed with PORTD
and PORTE)
PORTA
PORTC
PORTD
PORTE
RA0:RA7
(1)
RC0:RC7
(1)
RD0:RD7
(1)
RE0:RE2
(1)
PORTB
RB0:RB7
(1)
Note 1: See Table 1-3 for I/O port pin descriptions.
2: The on-chip voltage regulator is always enabled by default.
Data Memory
(3.8 Kbytes)
OSC1/CLKI
OSC2/CLKO
V
DD,VSS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
VDDCORE/VCAP
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ADC
EUSART2
MSSP2
Timer4
CTMU
HLVD
RTCC
ECCP1 ECCP2
ECCP3
CCP4 CCP5 CCP6 CCP7 CCP8
CCP9 CCP10
Timer5
Timer6 Timer8
8 MHz
INTOSC
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
Timing
Generation