Datasheet

PIC18F47J13 FAMILY
DS39974A-page 12 Preliminary  2010 Microchip Technology Inc.
1.1.3 EXPANDED MEMORY
The PIC18F47J13 family provides ample room for
application code, from 64 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last in excess of 10000 erase/write cycles. Data
retention without refresh is conservatively estimated to
be greater than 20 years.
The Flash program memory is readable and writable
during normal operation. The PIC18F47J13 family also
provides plenty of room for dynamic application data
with up to 3.8 Kbytes of data RAM.
1.1.4 EXTENDED INSTRUCTION SET
The PIC18F47J13 family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as C.
1.1.5 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the entire
family also aids in migrating to the next larger device.
The PIC18F47J13 family is also pin compatible with
other PIC18 families, such as the PIC18F4550,
PIC18F2450 and PIC18F46J50. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining the
same feature set.
1.2 Other Special Features
• Communications: The PIC18F47J13 family
incorporates a range of serial and parallel com-
munication peripherals. This device includes two
independent Enhanced USARTs and two Master
Synchronous Serial Port (MSSP) modules,
capable of both Serial Peripheral Interface (SPI)
and I
2
C™ (Master and Slave) modes of opera-
tion. The device also has a parallel port and can
be configured to serve as either a Parallel Master
Port (PMP) or as a Parallel Slave Port (PSP).
• CCP/ECCP Modules: All devices in the family
incorporate seven Capture/Compare/PWM (CCP)
modules and three Enhanced Capture/Com-
pare/PWM (ECCP) modules to maximize flexibility
in control applications. ECCPs offer up to four
PWM output signals each. The ECCPs also offer
many beneficial features, including polarity
selection, programmable dead time,
auto-shutdown and restart and Half-Bridge and
Full-Bridge Output modes.
• 10/12-Bit A/D Converter: This module incorpo-
rates programmable acquisition time, allowing for
a channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 30.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family
Devices
Devices in the PIC18F47J13 family are available in
28-pin and 44-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in
two ways:
• Flash program memory (two sizes: 64 Kbytes for
the PIC18FX6J13 and 128 Kbytes for
PIC18FX7J13)
• I/O ports (three bidirectional ports on 28-pin
devices, five bidirectional ports on 44-pin devices)
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for the PIC18F2XJ13 devices are listed in
Table 1-3. The pinouts for the PIC18F4XJ13 devices
are shown in Table 1-4.
The PIC18F47J13 family of devices provides an
on-chip voltage regulator to supply the correct voltage
levels to the core. Parts designated with an “F” part
number (such as PIC18F47J13) have the voltage
regulator enabled.
These parts can run from 2.15V-3.6V on V
DD, but should
have the V
DDCORE pin connected to VSS through a
low-ESR capacitor. Parts designated with an “LF” part
number (such as PIC18LF47J13) do not enable the volt-
age regulator nor support Deep Sleep mode. For “LF”
parts, an external supply of 2.0V-2.7V has to be supplied
to the V
DDCORE pin while 2.0V-3.6V can be supplied to
V
DD (VDDCORE should never exceed VDD).
For more details about the internal voltage regulator,
see Section 27.3 “On-Chip Voltage Regulator”.