Datasheet
PIC18F46J11 FAMILY
DS39932D-page 92 2011 Microchip Technology Inc.
RCREG1 EUSART1 Receive Register 0000 0000 71
TXREG1 EUSART1 Transmit Register 0000 0000 71
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 328
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 71, 329
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 71
RCREG2 EUSART2 Receive Register 0000 0000 71
TXREG2 EUSART2 Transmit Register 0000 0000 71
TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 328
EECON2 Program Memory Control Register 2 (not a physical register) ---- ---- 71
EECON1
— — WPROG FREE WRERR WREN WR — --00 x00- 71, 105
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 1111 1111 71, 128
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 0000 0000 71, 122
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 0000 0000 71, 125
IPR2 OSCFIP CM2IP CM1IP
— BCL1IP LVDIP TMR3IP CCP2IP 111- 1111 71, 127
PIR2 OSCFIF CM2IF CM1IF
— BCL1IF LVDIF TMR3IF CCP2IF 000- 0000 71, 121
PIE2 OSCFIE CM2IE CM1IE
— BCL1IE LVDIE TMR3IE CCP2IE 000- 0000 71, 124
IPR1 PMPIP
(5)
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 71, 126
PIR1 PMPIF
(5)
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 71, 120
PIE1 PMPIE
(5)
ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 71, 123
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 72, 329
OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 72, 42
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
T1DONE
T1GVAL T1GSS1 T1GSS0 0000 0x00 72, 202
RTCVALH RTCC Value Register Window High Byte, Based on RTCPTR<1:0> 0xxx xxxx 72
RTCVALL RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> 0xxx xxxx 72
T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/
T3DONE
T3GVAL T3GSS1 T3GSS0 0000 0x00 72, 216
TRISE
— — — — — TRISE2 TRISE1 TRISE0 ---- -111 72
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 72
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 72
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 72
TRISA TRISA7 TRISA6 TRISA5
— TRISA3 TRISA2 TRISA1 TRISA0 111- 1111 72
ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 0000 72, 231
ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 0000 72, 232
ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> xxxx xxxx 72
ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> xxxx xxxx 72
LATE
— — — — — LATE2 LATE1 LATE0 ---- -xxx 72
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 72
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 72
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 72
LATA LATA7 LATA6 LATA5
— LATA3 LATA2 LATA1 LATA0 xxx- xxxx 72
DMACON1 SSCON1 SSCON0 TXINC RXINC DUPLEX1 DUPLEX0 DLYINTEN DMAEN 0000 0000 72, 284
DMATXBUF SPI DMA Transmit Buffer xxxx xxxx 72
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes.
2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for
44-pin devices.
6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.