Datasheet

 2011 Microchip Technology Inc. DS39932D-page 91
PIC18F46J11 FAMILY
STATUS — — —NOV Z DCC---x xxxx 70, 96
TMR0H Timer0 Register High Byte 0000 0000 70
TMR0L Timer0 Register Low Byte xxxx xxxx 70
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 70, 197
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS
(2)
— SCS1 SCS0 0110 q-00 70, 44
CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 70, 362
CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 70, 362
RCON IPEN
—CMRI TO PD POR BOR 0-11 1100 70, 129
TMR1H Timer1 Register High Byte xxxx xxxx 70
TMR1L Timer1 Register Low Byte xxxx xxxx 70
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
RD16 TMR1ON 0000 0000 70, 201
TMR2 Timer2 Register 0000 0000 70
PR2 Timer2 Period Register 1111 1111 70
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 70, 213
SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 70
SSP1ADD MSSP1 Address Register (I
2
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
2
C Master mode) 0000 0000 70
SSP1MSK
(4)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 70, 295
SSP1STAT SMP CKE D/A
PSR/WUA BF 0000 0000 70, 292
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 70, 293
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 70, 294
GCEN ACKSTAT ADMSK5
(4)
ADMSK4
(4)
ADMSK3
(4)
ADMSK2
(4)
ADMSK1
(4)
SEN
ADRESH A/D Result Register High Byte xxxx xxxx 70
ADRESL A/D Result Register Low Byte xxxx xxxx 70
ADCON0 VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE
ADON 0000 0000 70, 351
ADCON1 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 70, 352
WDTCON REGSLP LVDSTAT ULPLVL
— DS ULPEN ULPSINK SWDTEN 1qq- q00 70, 406
PSTR1CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA 00-0 0001 70, 267
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 70
ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 71
CCPR1H Capture/Compare/PWM Register 1 HIgh Byte xxxx xxxx 71
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 71
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 71
PSTR2CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA 00-0 0001 71, 267
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 71
ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 71
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 71
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 71
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 71
CTMUCONH CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN — 0-00 000- 71
CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 00xx 71
CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 0000 0000 71
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 71
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes.
2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for
44-pin devices.
6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.