Datasheet

 2011 Microchip Technology Inc. DS39932D-page 65
PIC18F46J11 FAMILY
5.2 Master Clear (MCLR)
The Master Clear Reset (MCLR) pin provides a method
for triggering a hard external Reset of the device. A
Reset is generated by holding the pin low. PIC18
extended microcontroller devices have a noise filter in
the MCLR
Reset path, which detects and ignores small
pulses.
The MCLR
pin is not driven low by any internal Resets,
including the WDT.
5.3 Power-on Reset (POR)
A POR condition is generated on-chip whenever VDD
rises above a certain threshold. This allows the device
to start in the initialized state when V
DD is adequate for
operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a POR delay.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR
bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR
is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any POR.
5.4 Brown-out Reset (BOR)
“F” devices incorporate two types of BOR circuits: one
which monitors V
DDCORE and one which monitors VDD.
Only one BOR circuit can be active at a time. When in
normal Run mode, Idle or normal Sleep modes, the
BOR circuit that monitors V
DDCORE is active and will
cause the device to be held in BOR if V
DDCORE drops
below V
BOR (parameter D005). Once VDDCORE rises
back above V
BOR, the device will be held in Reset until
the expiration of the Power-up Timer, with period,
T
PWRT (parameter 33).
During Deep Sleep operation, the on-chip core voltage
regulator is disabled and V
DDCORE is allowed to drop to
ground levels. If the Deep Sleep BOR circuit is enabled
by the DSBOREN Configuration bit (CONFIG3L<2> = 1),
it will monitor V
DD. If VDD drops below the VDSBOR
threshold, the device will be held in a Reset state
similar to POR. All registers will be set back to their POR
Reset values and the contents of the DSGPR0 and
DSGPR1 holding registers will be lost.
Additionally, if any I/O pins had been configured as out-
puts during Deep Sleep, these pins will be tri-stated
and the device will no longer be held in Deep Sleep.
Once the V
DD voltage recovers back above the
V
DSBOR threshold, and once the core voltage regulator
achieves a V
DDCORE voltage above VBOR, the device
will begin executing code again normally, but the DS bit
in the WDTCON register will not be set. The device
behavior will be similar to hard cycling all power to the
device.
On “LF” devices, the V
DDCORE BOR circuit is always
disabled because the internal core voltage regulator is
disabled. Instead of monitoring VDDCORE, PIC18LF
devices in this family can use the V
DD BOR circuit to
monitor V
DD excursions below the VDSBOR threshold.
The V
DD BOR circuit can be disabled by setting the
DSBOREN bit = 0.
The V
DD BOR circuit is enabled when DSBOREN = 1
on “LF” devices, or on “F” devices while in Deep Sleep
with DSBOREN = 1. When enabled, the VDD BOR
circuit is extremely low power (typ. 40 nA) during nor-
mal operation above ~2.3V on V
DD. If VDD drops below
this DSBOR arming level when the V
DD BOR circuit is
enabled, the device may begin to consume additional
current (typ. 50 A) as internal features of the circuit
power up. The higher current is necessary to achieve
more accurate sensing of the V
DD level. However, the
device will not enter Reset until V
DD falls below the
V
DSBOR threshold.
5.4.1 DETECTING BOR
The BOR bit always resets to ‘0’ on any VDDCORE, BOR
or POR event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR
alone. A more reliable method is to
simultaneously check the state of both POR
and BOR.
This assumes that the POR
bit is reset to ‘1’ in software
immediately after any Power-on Reset event. If BOR
is
‘0’ while POR
is ‘1’, it can be reliably assumed that a
Brown-out Reset event has occurred.
If the voltage regulator is disabled (LF devices), the
V
DDCORE BOR functionality is disabled. In this case,
the BOR
bit cannot be used to determine a Brown-out
Reset event. The BOR
bit is still cleared by a Power-on
Reset event.