Datasheet

 2011 Microchip Technology Inc. DS39932D-page 493
PIC18F46J11 FAMILY
FIGURE 29-10: PARALLEL MASTER PORT READ TIMING DIAGRAM
TABLE 29-17: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Param.
No
Symbol Characteristics Min Typ Max Units
PM1 PMALL/PMALH Pulse Width — 0.5 T
CY —ns
PM2 Address Out Valid to PMALL/PMALH
Invalid (address setup time)
— 0.75 T
CY —ns
PM3 PMALL/PMALH Invalid to Address Out
Invalid (address hold time)
— 0.25 T
CY —ns
PM5 PMRD Pulse Width — 0.5 T
CY —ns
PM6 PMRD or PMENB Active to Data In Valid
(data setup time)
———ns
PM7 PMRD or PMENB Inactive to Data In Invalid
(data hold time)
———ns
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
System
PMALL/PMALH
PMD<7:0>
Address
PMA<13:18>
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated.
PMWR
PMCS
PMRD
Clock
PM2
PM3
PM6
PM7
PM5
PM1
Data
Address<7:0>