Datasheet

 2011 Microchip Technology Inc. DS39932D-page 489
PIC18F46J11 FAMILY
FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
TABLE 29-13: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 T
MCLMCLR Pulse-Width (low) 2 — — s—
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
2.8 4.0 5.3 ms —
32 T
OST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period — 1.0 — ms —
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
——3 TCY + 2 s (Note 1)
36 T
IRVST Time for Internal Reference
Voltage to become Stable
—20— s—
37 T
LVD High/Low-Voltage Detect
Pulse Width
—200— s—
38 T
CSD CPU Start-up Time — 200 — s (Note 2)
Note 1: The maximum T
IOZ is the lesser of (3 TCY + 2 s) or 700 s.
2: MCLR
rising edge to code execution, assuming TPWRT (and TOST if applicable) has already expired.
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 29-4 for load conditions.