Datasheet

 2011 Microchip Technology Inc. DS39932D-page 353
PIC18F46J11 FAMILY
The ANCON0 and ANCON1 registers are used to
configure the operation of the I/O pin associated with
each analog channel. Setting any one of the PCFG bits
configures the corresponding pin to operate as a digital
only I/O. Clearing a bit configures the pin to operate as
an analog input for either the A/D Converter or the
comparator module; all digital peripherals are disabled
and digital inputs read as ‘0’. As a rule, I/O pins that are
multiplexed with analog inputs default to analog
operation on device Resets.
In order to correctly perform A/D conversions on the V
BG
band gap reference (ADCON0<5:2> = 1111), the refer-
ence circuit must be powered on first. The VBGEN bit in
the ANCON1 register allows the firmware to manually
request that the band gap reference circuit should be
enabled. For best accuracy, firmware should allow a
settling time of at least 10 ms prior to performing the first
acquisition on this channel after enabling the band gap
reference.
The reference circuit may already have been turned on
if some other hardware module (such as comparators
or HLVD) has already requested it. In this case, the ini-
tial turn-on settling time may have already elapsed and
firmware does not need to wait as long before measur-
ing V
BG. Once the acquisition is complete, firmware
may clear the VBGEN bit, which will save a small
amount of power if no other modules are still requesting
the V
BG reference.
REGISTER 21-3: ANCON0: A/D PORT CONFIGURATION REGISTER 2 (BANKED F48h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG7
(1)
PCFG6
(1)
PCFG5
(1)
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PCFG<7:0>: Analog Port Configuration bits (AN<7:0>)
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0’
Note 1: These bits are not implemented on 28-pin devices.
REGISTER 21-4: ANCON1: A/D PORT CONFIGURATION REGISTER 1 (BANKED F49h)
R/W-0 r U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VBGEN — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
bit 7 bit 0
Legend: r = Reserved
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VBGEN: 1.2V Band Gap Reference Enable bit
1 = 1.2V band gap reference is powered on
0 = 1.2V band gap reference is turned off to save power (if no other modules are requesting it)
bit 6 Reserved: Always maintain as ‘0’ for lowest power consumption
bit 5 Unimplemented: Read as ‘0’
bit 4-0 PCFG<12:8>: Analog Port Configuration bits (AN<12:8>)
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0’