Datasheet

PIC18F46J11 FAMILY
DS39932D-page 312  2011 Microchip Technology Inc.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
2. SSPxIF is set. The MSSP module will wait for
the required start time before any other
operation takes place.
3. The user loads the SSPxBUF with the slave
address to transmit.
4. Address is shifted out of the SDAx pin until all
8 bits are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
7. The user loads the SSPxBUF with 8 bits of data.
8. Data is shifted out the SDAx pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPxCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
19.5.7 BAUD RATE
In I
2
C Master mode, the BRG reload value is placed in
the lower seven bits of the SSPxADD register
(Figure 19-19). When a write occurs to SSPxBUF, the
Baud Rate Generator will automatically begin counting.
The BRG counts down to 0 and stops until another
reload has taken place. The BRG count is decre-
mented twice per instruction cycle (T
CY) on the Q2 and
Q4 clocks. In I
2
C Master mode, the BRG is reloaded
automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK
), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD. The SSPADD BRG value of 0x00 is not
supported.