Datasheet

PIC18F46J11 FAMILY
DS39932D-page 252  2011 Microchip Technology Inc.
18.4 PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output.
Figure 18-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up a CCP
module for PWM operation, see Section 18.4.3
“Setup for PWM Operation”.
FIGURE 18-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 18-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
FIGURE 18-4: PWM OUTPUT
18.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using Equation 18-1:
EQUATION 18-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 (TMR4) is equal to PR2 (PR4), the
following three events occur on the next increment
cycle:
• TMR2 (TMR4) is cleared
• The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
18.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. Equation 18-2 is used to
calculate the PWM duty cycle in time.
EQUATION 18-2:
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 (PR4) and
TMR2 (TMR4) occurs (i.e., the period is complete). In
PWM mode, CCPRxH is a read-only register.
Note: Clearing the CCPxCON register will force
the output latch (depending on device
configuration) to the default low level. This
is not the LATx data latch.
CCPRxL
Comparator
Comparator
PRx
CCPxCON<5:4>
Q
S
R
CCPx
TRIS
Output Enable
CCPRxH
TMRx
2 LSbs latched
from Q clocks
Reset
Match
TMRx = PRx
Latch
09
(1)
Note 1: The two LSbs of the Duty Cycle register are held by a
2-bit latch that is part of the module’s hardware. It is
physically separate from the CCPRx registers.
Duty Cycle Register
Set CCPx pin
Duty Cycle
pin
Period
Duty Cycle
TMR2 (TMR4) = PR2 (TMR4)
TMR2 (TMR4) = Duty Cycle
TMR2 (TMR4) = PR2 (PR4)
Note: The Timer2 and Timer 4 postscalers (see
Section 14.0 “Timer2 Module” and
Section 16.0 “Timer4 Module”) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
T
OSC • (TMR2 Prescale Value)