Datasheet
2011 Microchip Technology Inc. DS39932D-page 223
PIC18F46J11 FAMILY
15.6 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
15.7 Resetting Timer3 Using the ECCP
Special Event Trigger
If ECCP1 or ECCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
The trigger from ECCP2 will also start an A/D conver-
sion if the A/D module is enabled (see Section 18.3.4
“Special Event Trigger” for more information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
TABLE 15-3: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The Special Event Triggers from the
ECCPx module will not set the TMR3IF
interrupt flag bit (PIR1<0>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
90
PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 92
PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 92
IPR2
OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 92
TMR3L Timer3 Register Low Byte 93
TMR3H Timer3 Register High Byte 93
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON
91
T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0
—
T3SYNC RD16 TMR3ON
93
T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/
T3DONE
T3GVAL T3GSS1 T3GSS0
92
TCLKCON
— — —
T1RUN
— —
T3CCP2 T3CCP1
94
PIR3
SSP2IF BCL2IF RC2IF
TX2IF
TMR4IF CTMUIF
TMR3GIF RTCCIF
92
PIE3
SSP2IE BCL2IE RC2IE
TX2IE
TMR4IE CTMUIE
TMR3GIE RTCCIE
92
IPR3
SSP2IP BCL2IP RC2IP
TX2IP
TMR4IP CTMUIP
TMR3GIP RTCCIP
92
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.