Datasheet

PIC18F46J11 FAMILY
DS39932D-page 218  2011 Microchip Technology Inc.
15.2 Timer3 Operation
Timer3 can operate in one of three modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
The operating mode is determined by the clock select
bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits
are cleared (= 00), Timer3 increments on every internal
instruction cycle (FOSC/4). When TMR3CSx = 01, the
Timer3 clock source is the system clock (F
OSC), and
when it is ‘10’, Timer3 works as a counter from the
external clock from the T3CKI pin (on the rising edge
after the first falling edge) or the Timer1 oscillator.
FIGURE 15-1: TIMER3 BLOCK DIAGRAM
TMR3H TMR3L
T3SYNC
T3CKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
Clock Input
2
Set Flag bit,
TMR3IF, on
Overflow
TMR3
(2)
TMR3ON
Note 1: ST Buffer is high-speed type when using T3CKI.
2: Timer3 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
T3G
FOSC/4
Internal
Clock
TMR3CS<1:0>
Synchronize
(3)
det
Sleep Input
TMR3GE
0
1
00
01
10
From Timer0
From Timer2
T3GPOL
D
Q
CK
Q
0
1
T3GVAL
T3GTM
Single Pulse
Acq. Control
T3GSPM
T3GGO/T3DONE
T3GSS<1:0>
10
00
01
FOSC
Internal
Clock
Match PR2
Overflow
R
D
EN
Q
Q1
RD
T3GCON
Data Bus
det
Interrupt
TMR3GIF
Set
T3CLK
FOSC/2
Internal
Clock
D
EN
Q
T3G_IN
TMR3ON
T3CKI