Datasheet

 2011 Microchip Technology Inc. DS39932D-page 137
PIC18F46J11 FAMILY
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
RA5/AN4/SS1/
HLVDIN/RP2
RA5 0 O DIG LATA<5> data output; not affected by analog input.
1 I TTL PORTA<5> data input; disabled when analog input enabled.
AN4 1 I ANA A/D input channel 4. Default configuration on POR.
SS1
1 I TTL Slave select input for MSSP1.
HLVDIN 1 I ANA High/Low-Voltage Detect external trip point reference input.
RP2 1 I ST Remappable Peripheral pin 2 input.
0 O DIG Remappable Peripheral pin 2 output.
OSC2/CLKO/
RA6
OSC2 x O ANA Main oscillator feedback output connection (HS mode).
CLKO x O DIG System cycle clock output (F
OSC/4) in RC and EC Oscillator
modes.
RA6 1 I TTL PORTA<6> data input.
0 O DIG LATA<6> data output.
OSC1/CLKI/RA7 OSC1 1 I ANA Main oscillator input connection.
CLKI 1 I ANA Main clock input connection.
RA7 1 I TTL PORTA<6> data input.
0 O DIG LATA<6> data output.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTA RA7 RA6 RA5
— RA3 RA2 RA1 RA0 87
LATA LAT7 LAT6 LAT5 — LAT3LAT2LAT1LAT0 87
TRISA TRIS7 TRIS6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 87
ANCON0 PCFG7
(1)
PCFG6
(1)
PCFG5
(1)
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 88
CMxCON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 87
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 88
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: These bits are only available in 44-pin devices.
TABLE 10-3: PORTA I/O SUMMARY (CONTINUED)
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: This bit is only available on 44-pin devices.