Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 61
PIC18F2682/2685/4682/4685
B0EIDL
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
B0EIDH
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
B0SIDL
(6)
2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu
B0SIDH
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
B0CON
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
TXBIE
(6)
2682 2685 4682 4685 ---0 00-- ---u uu-- ---u uu--
BIE0
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
BSEL0
(6)
2682 2685 4682 4685 0000 00-- 0000 00-- uuuu uu--
MSEL3
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
MSEL2
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
MSEL1
(6)
2682 2685 4682 4685 0000 0101 0000 0101 uuuu uuuu
MSEL0
(6)
2682 2685 4682 4685 0101 0000 0101 0000 uuuu uuuu
SDFLC
(6)
2682 2685 4682 4685 ---0 0000 ---0 0000 ---u uuuu
RXFCON1
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RXFCON0
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RXFBCON7
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RXFBCON6
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RXFBCON5
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RXFBCON4
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RXFBCON3
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RXFBCON2
(6)
2682 2685 4682 4685 0001 0001 0001 0001 uuuu uuuu
RXFBCON1
(6)
2682 2685 4682 4685 0001 0001 0001 0001 uuuu uuuu
RXFBCON0
(6)
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RXF15EIDL
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
RXF15EIDH
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
RXF15SIDL
(6)
2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu
RXF15SIDH
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
RXF14EIDL
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
RXF14EIDH
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
RXF14SIDL
(6)
2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu
RXF14SIDH
(6)
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.