Datasheet
© 2009 Microchip Technology Inc. DS39761C-page 53
PIC18F2682/2685/4682/4685
ADCON2 2682 2685 4682 4685 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H
2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 2682 2685
4682 4685 --00 0000 --00 0000 --uu uuuu
ECCPR1H 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
ECCPR1L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
ECCP1CON
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
BAUDCON 2682 2685 4682 4685 01-0 0-00 01-0 0-00 --uu uuuu
ECCP1DEL 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
ECCP1AS
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
CVRCON
2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
CMCON 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
TMR3H 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 2682 2685 4682 4685 0000 0000 uuuu uuuu uuuu uuuu
SPBRGH 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
SPBRG 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
RCREG 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
TXREG 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
TXSTA 2682 2685 4682 4685 0000 0010 0000 0010 uuuu uuuu
RCSTA 2682 2685 4682 4685 0000 000x 0000 000x uuuu uuuu
EEADRH 2682 2685 4682 4685 ---- --00 ---- --00 ---- --uu
EEADR 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
EEDATA 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
EECON2 2682 2685 4682 4685 0000 0000 0000 0000 0000 0000
EECON1 2682 2685 4682 4685 xx-0 x000 uu-0 u000 uu-0 u000
IPR3 2682 2685 4682 4685 1111 1111 1111 1111 uuuu uuuu
PIR3 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
PIE3 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
IPR2
2682 2685 4682 4685 11-1 1111 11-1 1111 uu-u uuuu
2682 2685
4682 4685 1--1 111- 1--1 111- u--u uuu-
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.