Datasheet
PIC18F2682/2685/4682/4685
DS39761C-page 52 © 2009 Microchip Technology Inc.
BSR 2682 2685 4682 4685 ---- 0000 ---- 0000 ---- uuuu
INDF2 2682 2685 4682 4685 N/A N/A N/A
POSTINC2 2682 2685 4682 4685 N/A N/A N/A
POSTDEC2 2682 2685 4682 4685 N/A N/A N/A
PREINC2 2682 2685 4682 4685 N/A N/A N/A
PLUSW2 2682 2685 4682 4685 N/A N/A N/A
FSR2H 2682 2685 4682 4685 ---- 0000 ---- 0000 ---- uuuu
FSR2L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 2682 2685 4682 4685 ---x xxxx ---u uuuu ---u uuuu
TMR0H 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
TMR0L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 2682 2685 4682 4685 1111 1111 1111 1111 uuuu uuuu
OSCCON 2682 2685 4682 4685 0100 q000 0100 00q0 uuuu uuqu
HLVDCON 2682 2685 4682 4685 0-00 0101 0-00 0101 0-uu uuuu
WDTCON 2682 2685 4682 4685 ---- ---0 ---- ---0 ---- ---u
RCON
(4)
2682 2685 4682 4685 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 2682 2685 4682 4685 0000 0000 u0uu uuuu uuuu uuuu
TMR2 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
PR2 2682 2685 4682 4685 1111 1111 1111 1111 1111 1111
T2CON 2682 2685 4682 4685 -000 0000 -000 0000 -uuu uuuu
SSPBUF 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
SSPCON1 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
SSPCON2 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu
ADRESH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 2682 2685 4682 4685 --00 0000 --00 0000 --uu uuuu
ADCON1 2682 2685 4682 4685 --00 0qqq --00 0qqq --uu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.