Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 479
PIC18F2682/2685/4682/4685
SPI Mode (Slave Mode with CKE = 0) ..................... 196
SPI Mode (Slave Mode with CKE = 1) ..................... 196
Stop Condition Receive or Transmit Mode .............. 222
Synchronous Reception (Master Mode, SREN) ...... 246
Synchronous Transmission ...................................... 244
Synchronous Transmission
(Through TXEN) .............................................. 245
Time-out Sequence on POR w/PLL Enabled
(MCLR
Tied to VDD) ........................................... 49
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1 ....................... 48
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 2 ...................... 48
Time-out Sequence on Power-up
(MCLR
Tied to VDD, VDD Rise Tpwrt) ................ 48
Timer0 and Timer1 External Clock .......................... 441
Transition for Entry to Idle Mode ................................ 40
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 39
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 357
Transition for Wake From Idle to Run Mode .............. 40
Transition for Wake From Sleep (HSPLL) ................. 39
Transition From RC_RUN Mode
to PRI_RUN Mode ............................................. 38
Transition From SEC_RUN Mode
to PRI_RUN Mode (HSPLL) .............................. 37
Transition to RC_RUN Mode ..................................... 38
Timing Diagrams and Specifications ................................ 437
AC Characteristics
Internal RC Accuracy ....................................... 438
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 442
CLKO and I/O Requirements ................................... 439
EUSART Synchronous Receive Requirements ....... 452
EUSART Synchronous Transmission
Requirements ................................................. 452
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 444
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 445
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 446
Example SPI Mode Requirements
(Slave Mode, CKE = 1) .................................... 447
External Clock Requirements .................................. 437
I
2
C Bus Data Requirements (Slave Mode) .............. 449
I
2
C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 448
Master SSP I
2
C Bus Data Requirements ................ 451
Master SSP I
2
C Bus Start/Stop Bits Requirements . 450
Parallel Slave Port Requirements
(PIC18F4682/4685) ......................................... 443
PLL Clock ................................................................ 438
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 440
Timer0 and Timer1 External
Clock Requirements ........................................ 441
Top-of-Stack Access .......................................................... 64
TRISE Register
PSPMODE Bit ......................................................... 140
TSTFSZ ........................................................................... 405
Two-Speed Start-up ................................................. 345, 357
Two-Word Instructions
Example Cases ......................................................... 68
TXSTA Register
BRGH Bit ................................................................. 233
V
Voltage Reference Specifications .................................... 433
W
Watchdog Timer (WDT) ........................................... 345, 355
Associated Registers ............................................... 356
Control Register ....................................................... 355
Programming Considerations .................................. 355
WCOL ...................................................... 217, 218, 219, 222
WCOL Status Flag ................................... 217, 218, 219, 222
WWW Address ................................................................ 481
WWW, On-Line Support ...................................................... 7
X
XORLW ........................................................................... 405
XORWF ........................................................................... 406