Datasheet

PIC18F2682/2685/4682/4685
DS39761C-page 478 © 2009 Microchip Technology Inc.
T
T0CON Register
PSA Bit ..................................................................... 151
T0CS Bit ...................................................................150
T0PS2:T0PS0 Bits ...................................................151
T0SE Bit ................................................................... 150
Table Reads/Table Writes .................................................. 66
TBLRD .............................................................................403
TBLWT .............................................................................404
Time-out in Various Situations (table) ................................47
Timer0 .............................................................................. 149
Associated Registers ...............................................151
Clock Source Edge Select (T0SE Bit) ...................... 150
Clock Source Select (T0CS Bit) ............................... 150
Operation ................................................................. 150
Overflow Interrupt .................................................... 151
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 150
Timer1 .............................................................................. 153
16-Bit Read/Write Mode ........................................... 155
Associated Registers ...............................................157
Interrupt .................................................................... 156
Operation ................................................................. 154
Oscillator .................................................................. 155
Layout Considerations ..................................... 156
Resetting, Using a Special Event Trigger
Output (CCP1) .................................................156
Special Event Trigger (ECCP1) ............................... 176
Use as a Real-Time Clock .......................................156
Timer2 .............................................................................. 159
Associated Registers ...............................................160
Interrupt .................................................................... 160
Operation ................................................................. 159
Output ...................................................................... 160
PR2 Register .................................................... 171, 177
TMR2 to PR2 Match Interrupt .................................. 171
Timer3 .............................................................................. 161
16-Bit Read/Write Mode ........................................... 163
Associated Registers ...............................................163
Operation ................................................................. 162
Oscillator .................................................. 153, 161, 163
Overflow Interrupt .................................................... 163
Special Event Trigger (ECCP1) ............................... 163
TMR3H Register .............................................. 153, 161
TMR3L Register ............................................... 153, 161
Timing Diagrams
A/D Conversion ........................................................ 454
Acknowledge Sequence .......................................... 222
Asynchronous Reception ......................................... 241
Asynchronous Transmission .................................... 239
Asynchronous Transmission (Back-to-Back) ........... 239
Automatic Baud Rate Calculation ............................ 237
Auto-Wake-up Bit (WUE) During Normal Operation 242
Auto-Wake-up Bit (WUE) During Sleep ................... 242
Baud Rate Generator with Clock Arbitration ............ 216
BRG Overflow Sequence ......................................... 237
BRG Reset Due to SDA Arbitration
During Start Condition ...................................... 225
Brown-out Reset (BOR) ........................................... 440
Bus Collision During a Repeated Start Condition
(Case 1) ........................................................... 226
Bus Collision During a Repeated Start Condition
(Case 2) ........................................................... 226
Bus Collision During a Start Condition
(SCL = 0) ......................................................... 225
Bus Collision During a Start Condition
(SDA Only) ...................................................... 224
Bus Collision During a Stop Condition
(Case 1) ........................................................... 227
Bus Collision During a Stop Condition
(Case 2) ........................................................... 227
Bus Collision for Transmit and
Acknowledge ................................................... 223
Capture/Compare/PWM (All CCP Modules) ............ 442
CLKO and I/O .......................................................... 439
Clock Synchronization ............................................. 209
Clock/Instruction Cycle .............................................. 67
EUSART Synchronous Receive
(Master/Slave) ................................................. 452
EUSART Synchronous Transmission
(Master/Slave) ................................................. 452
Example SPI Master Mode (CKE = 0) ..................... 444
Example SPI Master Mode (CKE = 1) ..................... 445
Example SPI Slave Mode (CKE = 0) ....................... 446
Example SPI Slave Mode (CKE = 1) ....................... 447
External Clock (All Modes Except PLL) ................... 437
Fail-Safe Clock Monitor ........................................... 359
First Start Bit Timing ................................................ 217
Full-Bridge PWM Output .......................................... 181
Half-Bridge PWM Output ......................................... 180
High/Low-Voltage Detect Characteristics ................ 434
High-Voltage Detect (VDIRMAG = 1) ...................... 272
I
2
C Bus Data ............................................................ 448
I
2
C Bus Start/Stop Bits ............................................ 448
I
2
C Master Mode (7 or 10-Bit Transmission) ........... 220
I
2
C Master Mode (7-Bit Reception) .......................... 221
I
2
C Slave Mode (10-Bit Reception, SEN = 0) .......... 206
I
2
C Slave Mode (10-Bit Reception, SEN = 1) .......... 211
I
2
C Slave Mode (10-Bit Transmission) .................... 207
I
2
C Slave Mode (7-Bit Reception, SEN = 0) ............ 204
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............ 210
I
2
C Slave Mode (7-Bit Transmission) ...................... 205
I
2
C Slave Mode General Call Address Sequence (7 or
10-Bit Address Mode) ...................................... 212
Low-Voltage Detect (VDIRMAG = 0) ....................... 271
Master SSP I
2
C Bus Data ........................................ 450
Master SSP I
2
C Bus Start/Stop Bits ........................ 450
Parallel Slave Port (PIC18F4682/4685) ................... 443
Parallel Slave Port (PSP) Read ............................... 147
Parallel Slave Port (PSP) Write ............................... 147
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 186
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 186
PWM Direction Change ........................................... 183
PWM Direction Change at Near 100% Duty Cycle .. 183
PWM Output ............................................................ 171
Repeated Start Condition ........................................ 218
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 440
Send Break Character Sequence ............................ 243
Slave Synchronization ............................................. 195
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT) ............................................ 49
SPI Mode (Master Mode) ......................................... 194