Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 477
PIC18F2682/2685/4682/4685
RXBnEIDL (Receive Buffer n
Extended Identifier, Low Byte) ......................... 294
RXBnSIDH (Receive Buffer n
Standard Identifier, High Byte) ......................... 293
RXBnSIDL (Receive Buffer n
Standard Identifier, Low Byte) ......................... 294
RXERRCNT (Receive Error Count) ......................... 296
RXFBCONn (Receive Filter Buffer Control n) .......... 309
RXFCONn (Receive Filter Control n) ....................... 308
RXFnEIDH (Receive Acceptance Filter n
Extended Identifier, High Byte) ........................ 306
RXFnEIDL (Receive Acceptance Filter n
Extended Identifier, Low Byte) ......................... 306
RXFnSIDH (Receive Acceptance Filter n
Standard Identifier Filter, High Byte) ................ 305
RXFnSIDL (Receive Acceptance Filter n
Standard Identifier Filter, Low Byte) ................ 305
RXMnEIDH (Receive Acceptance Mask n
Extended Identifier Mask, High Byte) .............. 307
RXMnEIDL (Receive Acceptance Mask n
Extended Identifier Mask, Low Byte) ............... 307
RXMnSIDH (Receive Acceptance Mask n
Standard Identifier Mask, High Byte) ............... 306
RXMnSIDL (Receive Acceptance Mask n
Standard Identifier Mask, Low Byte) ................ 307
SDFLC (Standard Data Bytes Filter Length Count) . 308
SSPCON1 (MSSP Control 1, I
2
C Mode) ................. 200
SSPCON1 (MSSP Control 1, SPI Mode) ................. 191
SSPCON2 (MSSP Control 2, I
2
C Mode) ................. 201
SSPSTAT (MSSP Status, I
2
C Mode) ....................... 199
SSPSTAT (MSSP Status, SPI Mode) ...................... 190
STATUS ..................................................................... 89
STKPTR (Stack Pointer) ............................................ 65
T0CON (Timer0 Control) .......................................... 149
T1CON (Timer1 Control) .......................................... 153
T2CON (Timer2 Control) .......................................... 159
T3CON (Timer3 Control) .......................................... 161
TRISE (PORTE/PSP Control) .................................. 144
TXBIE (Transmit Buffers Interrupt Enable) .............. 321
TXBnCON (Transmit Buffer n Control) .................... 284
TXBnDLC (Transmit Buffer n
Data Length Code) .......................................... 287
TXBnDm (Transmit Buffer n
Data Field Byte m) ........................................... 286
TXBnEIDH (Transmit Buffer n
Extended Identifier, High Byte) ........................ 285
TXBnEIDL (Transmit Buffer n
Extended Identifier, Low Byte) ......................... 286
TXBnSIDH (Transmit Buffer n
Standard Identifier, High Byte) ......................... 285
TXBnSIDL (Transmit Buffer n
Standard Identifier, Low Byte) ......................... 285
TXERRCNT (Transmit Error Count) ........................ 287
TXSTA (Transmit Status and Control) ..................... 230
WDTCON (Watchdog Timer Control) ...................... 356
RESET ............................................................................. 395
Resets ........................................................................ 43, 345
Brown-out Reset (BOR) ........................................... 345
Oscillator Start-up Timer (OST) ............................... 345
Power-on Reset (POR) ............................................ 345
Power-up Timer (PWRT) ......................................... 345
RETFIE ............................................................................ 396
RETLW ............................................................................ 396
RETURN .......................................................................... 397
Return Address Stack ........................................................ 64
Associated Registers ................................................. 64
Return Stack Pointer (STKPTR) ........................................ 65
Revision History ............................................................... 465
RLCF ............................................................................... 397
RLNCF ............................................................................. 398
RRCF ............................................................................... 398
RRNCF ............................................................................ 399
S
SCK ................................................................................. 189
SDI ................................................................................... 189
SDO ................................................................................. 189
SEC_IDLE Mode ............................................................... 40
SEC_RUN Mode ................................................................ 36
Serial Clock, SCK ............................................................ 189
Serial Data In (SDI) .......................................................... 189
Serial Data Out (SDO) ..................................................... 189
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 399
Slave Select (SS
) ............................................................. 189
SLEEP ............................................................................. 400
Sleep
OSC1 and OSC2 Pin States ...................................... 33
Software Simulator (MPLAB SIM) ................................... 417
Special Event Trigger. See Compare (CCP1/ECCP1 Mod-
ules).
Special Event Trigger. See Compare (ECCP1 Module).
Special Function Registers
Map ...................................................................... 72–77
SPI Mode (MSSP) ........................................................... 189
Associated Registers ............................................... 197
Bus Mode Compatibility ........................................... 197
Effects of a Reset .................................................... 197
Enabling SPI I/O ...................................................... 193
Master Mode ............................................................ 194
Master/Slave Connection ........................................ 193
Operation ................................................................. 192
Operation in Power-Managed Modes ...................... 197
Serial Clock ............................................................. 189
Serial Data In ........................................................... 189
Serial Data Out ........................................................ 189
Slave Mode .............................................................. 195
Slave Select ............................................................. 189
Slave Select Synchronization .................................. 195
SPI Clock ................................................................. 194
Typical Connection .................................................. 193
SS
.................................................................................... 189
SSPOV ............................................................................ 219
SSPOV Status Flag ......................................................... 219
SSPSTAT Register
R/W
Bit ............................................................ 202, 203
Stack Full/Underflow Resets .............................................. 66
Status Register .................................................................. 89
SUBFSR .......................................................................... 411
SUBFWB ......................................................................... 400
SUBLW ............................................................................ 401
SUBULNK ........................................................................ 411
SUBWF ............................................................................ 401
SUBWFB ......................................................................... 402
SWAPF ............................................................................ 402