Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 447
PIC18F2682/2685/4682/4685
FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 27-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
↓ to SCK ↓ or SCK ↑ Input TCY —ns
71 T
SCH SCK Input High Time Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A T
B2B Last Clock Edge of Byte 1 to the fIrst Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 T
DOR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
76 T
DOF SDO Data Output Fall Time — 25 ns
77 T
SSH2DOZSS↑ to SDO Output High-Impedance 10 50 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK
Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V
82 T
SSL2DOV SDO Data Output Valid after SS ↓
Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V
83 T
SCH2SSH,
T
SCL2SSH
SS
↑ after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of parameter 73A.
2: Only if parameter 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
74
75, 76
MSb
bit 6 - - - - - -1
LSb
77
bit 6 - - - -1
LSb In
80
83
Note: Refer to Figure 27-4 for load conditions.
MSb In