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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 8-Bit 40 MHz I/O number 25
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PIC18F2682/2685/4682/4685
DS39761C-page 308 © 2009 Microchip Technology Inc.
REGISTER 23-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 ≤ n ≤ 1]
(1)
RXFCON0
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN
RXFCON1
R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RXFnEN: Receive Filter n Enable bits
0 = Filter is disabled
1 = Filter is enabled
Note 1: This register is available in Mode 1 and 2 only.
Note: Register 23-46 through Register 23-51 are writable in Configuration mode only.
REGISTER 23-46: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER
(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — FLC4 FLC3 FLC2 FLC1 FLC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 FLC4:FLC0: Filter Length Count bits
Mode 0:
Not used; forced to ‘00000’.
00000-10010 = 0 18 bits are available for standard data byte filter. Actual number of bits used
depends on DLC3:DLC0 bits (RXBnDLC<3:0> or BnDLC<3:0> if configured
as RX buffer) of message being received.
If DLC3:DLC0 = 0000 No bits will be compared with incoming data bits.
If DLC3:DLC0 = 0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC2:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
If DLC3:DLC0 = 0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC3:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
If DLC3:DLC0 = 0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC4:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
Note 1: This register is available in Mode 1 and 2 only.