Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 263
PIC18F2682/2685/4682/4685
20.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
V
SS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 20-4: COMPARATOR ANALOG INPUT MODEL
TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
VA
R
S < 10k
A
IN
CPIN
5 pF
V
DD
VT = 0.6V
V
T = 0.6V
R
IC
ILEAKAGE
±500 nA
V
SS
Legend: CPIN = Input Capacitance
V
T = Threshold Voltage
I
LEAKAGE = Leakage Current at the pin due to various junctions
R
IC = Interconnect Resistance
R
S = Source Impedance
VA = Analog Voltage
Comparator
Input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
CMCON
(3)
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53
CVRCON
(3)
CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54
IPR2
OSCFIP CMIP
(2)
— EEIP BCLIP HLVDIP TMR3IP ECCP1IP
(2)
53
PIR2
OSCFIF CMIF
(2)
— EEIF BCLIF HLVDIF TMR3IF ECCP1IF
(2)
54
PIE2
OSCFIE CMIE
(2)
— EEIE BCLIE HLVDIE TMR3IE ECCP1IE
(2)
54
PORTA RA7
(1)
RA6
(1)
RA5 RA4 RA3 RA2 RA1 RA0 54
LATA LATA7
(1)
LATA6
(1)
LATA Data Output Register 54
TRISA TRISA7
(1)
TRISA6
(1)
PORTA Data Direction Register 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA pins are enabled based on oscillator configuration.
2: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices.
3: These registers are unimplemented on PIC18F2682/2685 devices.