Datasheet

PIC18F2682/2685/4682/4685
DS39761C-page 250 © 2009 Microchip Technology Inc.
REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0
(1)
R/W-q
(1)
R/W-q
(1)
R/W-q
(1)
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (V
REF- source)
1 = VREF- (AN2)
0 = AV
SS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = V
REF+ (AN3)
0 = AV
DD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN bit in Configuration Register 3H.
When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on PIC18F4682/4685 devices.
A = Analog input D = Digital I/O
PCFG3:
PCFG0
AN10 AN9 AN8 AN7
(2)
AN6
(2)
AN5
(2)
AN4 AN3 AN2 AN1 AN0
0000
(1)
AAAAAAAAAAA
0001 AAAAAAAAAAA
0010 AAAAAAAAAAA
0011 AAAAAAAAAAA
0100 AAAAAAAAAAA
0101 DAAAAAAAAAA
0110 DDAAAAAAAAA
0111
(1)
DDDAAAAAAAA
1000 DDDDAAAAAAA
1001 DDDDDAAAAAA
1010 DDDDDDAAAAA
1011 DDDDDDDAAAA
1100 DDDDDDDDAAA
1101 DDDDDDDDDAA
1110 DDDDDDDDDDA
1111 DDDDDDDDDDD