Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 245
PIC18F2682/2685/4682/4685
FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
TXREG EUSART Transmit Register 53
TXSTA CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL —SCKPBRG16— WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear.