Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 239
PIC18F2682/2685/4682/4685
FIGURE 18-4: ASYNCHRONOUS TRANSMISSION
FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
BRG Output
(Shift Clock)
TX
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
(pin)
Word 1
Stop bit
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
(pin)
Start bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1
PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1
PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
TXREG EUSART Transmit Register 53
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear.