Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 173
PIC18F2682/2685/4682/4685
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
RCON IPEN SBOREN
(2)
— RI TO PD POR BOR 52
PIR1
PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1
PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
TRISB PORTB Data Direction Register 54
TRISC PORTC Data Direction Register 54
TMR2 Timer2 Register 52
PR2 Timer2 Period Register 52
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52
CCPR1L Capture/Compare/PWM Register 1 Low Byte 53
CCPR1H Capture/Compare/PWM Register 1 High Byte 53
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
ECCPR1L
(1)
Enhanced Capture/Compare/PWM Register 1 Low Byte 53
ECCPR1H
(1)
Enhanced Capture/Compare/PWM Register 1 High Byte 53
ECCP1CON
(1)
EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: These bits or registers are available on PIC18F4682/4685 devices only.
2: The SBOREN bit is only available when CONFIG2L<1:0> =
01; otherwise, it is disabled and reads as ‘0’.