Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 171
PIC18F2682/2685/4682/4685
15.4 PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP1 pin an output.
Figure 15-3 shows a simplified block diagram of the
CCP1 module in PWM mode.
For a step-by-step procedure on how to set up the
CCP1 module for PWM operation, see Section 15.4.4
“Setup for PWM Operation”.
FIGURE 15-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
FIGURE 15-4: PWM OUTPUT
15.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using the following formula.
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period].
When TMR1 (TMR3) is equal to PR2 (PR4), the
following three events occur on the next increment
cycle:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
15.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
EQUATION 15-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Note: Clearing the CCP1CON register will force
the RC2 output latch to the default low
level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R
Q
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
PORTC<2>
Note: The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
T
OSC • (TMR2 Prescale Value)