Datasheet

PIC18F2682/2685/4682/4685
DS39761C-page 170 © 2009 Microchip Technology Inc.
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
RCON IPEN SBOREN
(2)
— RI TO PD POR BOR 52
IPR1
PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR2
OSCFIP
CMIP
(1)
— EEIP BCLIP HLVDIP TMR3IP ECCP1IP
(1)
54
PIR2
OSCFIF
CMIF
(1)
— EEIF BCLIF HLVDIF TMR3IF ECCP1IF
(1)
54
PIE2
OSCFIE
CMIE
(1)
— EEIE BCLIE HLVDIE TMR3IE ECCP1IE
(1)
53
TRISB PORTB Data Direction Register 54
TRISC PORTC Data Direction Register 54
TMR1L Timer1 Register Low Byte 52
TMR1H Timer1 Register High Byte 52
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 52
TMR3H Timer3 Register High Byte 53
TMR3L Timer3 Register Low Byte 53
T3CON RD16 T3ECCP1
(1)
T3CKPS1 T3CKPS0 T3CCP1
(1)
T3SYNC TMR3CS TMR3ON 53
CCPR1L Capture/Compare/PWM Register 1 Low Byte 53
CCPR1H Capture/Compare/PWM Register 1 High Byte 53
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
ECCPR1L
(1)
Enhanced Capture/Compare/PWM Register 1 Low Byte 53
ECCPR1H
(1)
Enhanced Capture/Compare/PWM Register 1 High Byte 53
ECCP1CON
(1)
EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
Note 1: These bits or registers are available on PIC18F4682/4685 devices only.
2: The SBOREN bit is only available when CONFIG2L<1:0> =
01; otherwise, it is disabled and reads as ‘0’.