Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 147
PIC18F2682/2685/4682/4685
FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTD
(1)
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 54
LATD
(1)
LATD Data Output Register 54
TRISD
(1)
PORTD Data Direction Register 54
PORTE
(1)
— — — — RE3 RE2 RE1 RE0 54
LATE
(1)
— — — — — LATE Data Output Register 54
TRISE
(1)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 54
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF
(2)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE
(2)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP
(2)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52
CMCON
(1)
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers are available on PIC18F4682/4685 devices only.
2: These bits are unimplemented on PIC18F2682/2685 devices and read as ‘0’.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>