Datasheet

PIC18F2682/2685/4682/4685

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

PORTA RA7

(1)

RA6

(1)

RA5 RA4 RA3 RA2 RA1 RA0 54

LATA LATA7

(1)

LATA6

(1)

LATA Data Output Register 54

TRISA TRISA7

(1)

TRISA6

(1)

PORTA Data Direction Register 54

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52

CMCON

(2)

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53

CVRCON

(2)

CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.

Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

2: These registers are unimplemented on PIC18F2682/2685 devices.