Datasheet

PIC18F2682/2685/4682/4685
DS39761C-page 124 © 2009 Microchip Technology Inc.
REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIE CMIE
(1)
— EEIE BCLIE HLVDIE TMR3IE ECCP1IE
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
(1)
1 = Enabled
0 = Disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 0 ECCP1IE: ECCP1 Interrupt Enable bit
(1)
1 = Enabled
0 =Disabled
Note 1: These bits are available on PIC18F4682/4685 devices only.